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19-2192; Rev 0; 10/01
Dual-Rate Fibre Channel Repeaters
General Description
The MAX3772-MAX3775 are dual-rate (1.0625Gbps and 2.125Gbps) fibre channel repeaters. They are optimized for use in fibre channel arbitrated loop applications and operate from a +3.3V supply. The MAX3772-MAX3775 exceed fibre channel jitter tolerance requirements and can recover data signals with up to 0.7 unit interval (UI) jitter. The circuit's fully integrated phase-locked loop (PLL) provides a frequency lock indication and does not need an external reference clock. These repeaters provide low-jitter CML clock and data outputs, and are pin compatible with the MAX3770 repeater (except RATESEL pin and exposed paddle). The MAX3773/MAX3774 can also be used for impedance transformation between 100 (differential) and 150 (differential) systems. To reduce the number of external components, all signal inputs and outputs are internally terminated. The MAX3772-MAX3775 are available in 16-pin QSOP-EP packages.
Features
o Pin Selectable 1.0625Gbps/2.125Gbps Dual-Rate Fibre Channel Operation o Exceeds Fibre Channel Jitter Tolerance Requirements o 1400mV Differential Output Swing o +3.0V to +3.6V Operation o No Reference Clock Required o Frequency Lock Indication o 290mW Power Consumption (MAX3775) at +3.3V o 100/150 (differential) Input/Output Terminations
MAX3772-MAX3775
Ordering Information
PART MAX3772CEE MAX3773CEE MAX3774CEE MAX3775CEE TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 16 QSOP-EP 16 QSOP-EP 16 QSOP-EP 16 QSOP-EP
Applications
1.0625Gbps/2.125Gbps Dual-Rate Fibre Channel Fibre Channel Data Storage Systems Storage Area Networks Fibre Channel Hubs 100/150 (Differential) Impedance Transformation
Pin Configuration appears at end of data sheet. Selector Guide appears at end of data sheet.
Typical Operating Circuits
0.047F
LOUT+
LOCK
LIN-
LIN+
LOUT+
LINSEL
LOUT-
CLK+ CLK-
IN+
OUT+
Zo = 75 Zo = 75
IN+ IN-
MAX3750
INVCC SEL OUTGND
MAX3775
RATESEL
OUT+ OUT-
Zo = 75 Zo = 75
IN+
LOUT-
OUT+
MAX3750
INVCC OUTGND
CLKEN
3.3V 0.1F
3.3V 0.1F
GND
VCC
3.3V 0.1F
PORT BYPASS CIRCUIT
FIBRE CHANNEL REPEATER
PORT BYPASS CIRCUIT
________________________________________________________________ Maxim Integrated Products
LIN+
CF+
CF-
1
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Dual-Rate Fibre Channel Repeaters MAX3772-MAX3775
ABSOLUTE MAXIMUM RATINGS
VCC ........................................................................-0.5V to +5.0V Pin Voltage Levels (IN, CF, RATESEL, CLKEN, LOCK) .....................-0.5V to (VCC + 0.5V) Current into LOCK...............................................-1mA to +10mA CML Output Currents (OUT, CLK), ROUT = 75 ........ +22mA CML Output Currents (OUT, CLK), ROUT = 50 ........ +33mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP-EP (derate 18.9mW/C above +70C) ...702mW Operating Junction Temperature Range ...........-55C to +150C Operating Temperature Range .........................-55C to +110C Storage Temperature Range ............................-55C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, 8B/10B data coding, CF = 0.047F, lock pin loaded with 15k resistor, all high-speed inputs and outputs AC-coupled, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.)
PARAMETER CLKEN = GND Supply Current (Note 1) CLKEN = VCC CONDITIONS MAX3772/MAX3773 MAX3774/MAX3775 MAX3772/MAX3773 MAX3774/MAX3775 MAX3772/MAX3773, 100 terminated Figure 1 MAX3774/MAX3775, 150 terminated MAX3772/MAX3773 100 terminated MAX3774/MAX3775, 150 terminated 1000 1000 1000 -100 -100 136 75 100 50 2.4 -50 -0.3 2 200 VCC 0.45 (Note 2) Input = CJTPAT (Note 3) 500 VCC 50 0.8 VCC + 0.3 2200 130 75 1400 1400 1400 1800 1800 mVp-p 1800 +100 +100 325 160 175 100 0.4 ppm ps ps ps V V A V V mVp-p V V s MIN 80 68 115 95 1000 TYP 101 88 146 121 1400 MAX 140 124 195 164 1800 mVp-p mA UNITS
Differential Voltage Signal at OUT+
Differential Voltage Signal at CLK+
Figure 1
Input Data Rate Range Input Edge Speed Data Transition Time (OUT) Clock Transition Time (CLK) LOCK Output Low LOCK Output High CLKEN, RATESEL Input Current CLKEN, RATESEL Input Low CLKEN, RATESEL Input High Differential Input Voltage Swing Input Common-Mode Voltage Differential Voltage across CF+ CDR Lock Time
1.0625Gbps operation, RATESEL = GND 2.125Gbps operation, RATESEL = VCC 20% to 80% 1.0625Gbps operation 20% to 80% 2.125Gbps operation 20% to 80% (Note 2) 20% to 80% (Note 2) IOL = +250A (sinking) IOH = -100A (sourcing)
2
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Dual-Rate Fibre Channel Repeaters
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, 8B/10B data coding, CF = 0.047F, lock pin loaded with 15k resistor, all high-speed inputs and outputs AC-coupled, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.)
PARAMETER Differential Input Resistance (IN+) Differential Output Resistance (OUT+, CLK+) Supply Noise Tolerance (Note 4) MAX3772/MAX3774 MAX3773/MAX3775 MAX3772/MAX3773 MAX3774/MAX3775 10Hz f < 100Hz 100Hz f < 1MHz CONDITIONS MIN 78 118 78 118 TYP 100 150 100 150 100 40 10 4.4 2.8 2.9 22 48 99 f = 85kHz Sinusoidal Component of Jitter Tolerance (BER = 10-12) Total High-Frequency Jitter Tolerance Jitter Transfer Bandwidth Jitter Transfer Peaking Propagation Delay Clock to Q Delay Falling clock to data transition Input = K28.7 (Note 5) Random Jitter Generation at OUT+ and CLK+ Deterministic Jitter on OUT+ Total Jitter at OUT+ Sinusoidal Component of Jitter Tolerance (BER = 10-12) Total High-Frequency Jitter Tolerance Jitter Transfer Bandwidth Jitter Transfer Peaking Propagation Delay Clock to Q Delay Falling clock to data transition 200 510 Input = CRPAT (Note 6) Input = CRPAT (Notes 6, 7) Input = K28.5 (Note 8) Input = RPAT (Notes 7, 9) Input = RPAT (Notes 7, 9, 10) f = 42.5kHz Input = CJTPAT (Notes 3, 7) f = 635kHz f = 5MHz Input = CJTPAT (Notes 3, 7, 9) Measured with 50% edge density (Note 11) 1.5 0.1 0.1 0.7 6 0.05 5 740 UI MHz dB ns ps UI 150 OPERATION AT 1.0625Gbps (Note 2) 6.2 3.6 4.9 40 75 160 psp-p psp-p psRMS Input = CJTPAT (Notes 3, 7) f = 1270kHz f = 10MHz Input = CJTPAT (Notes 3, 7, 9) Measured with 50% edge density (Note 11) 1.0 280 1.5 0.1 0.1 0.7 11 0.05 1.5 300 UI MHz dB ns ps UI psp-p psp-p psRMS mVp-p MAX 122 182 122 182 UNITS
MAX3772-MAX3775
1MHz f < 2.5GHz OPERATION AT 2.125Gbps (Note 2) Input = K28.7 (Note 5) Random Jitter Generation at Input = CRPAT (Note 6) OUT+ and CLK+ Input = CRPAT (Notes 6, 7) Deterministic Jitter on OUT+ Total Jitter at OUT+ Input = K28.5 (Note 8) Input = RPAT (Notes 7, 9) Input = RPAT (Notes 7, 9, 10)
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3
Dual-Rate Fibre Channel Repeaters MAX3772-MAX3775
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, 8B/10B data coding, CF = 0.047F, lock pin loaded with 15k resistor, all high-speed inputs and outputs AC-coupled, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) Note 1: Supply current includes output currents. Note 2: Guaranteed by design and characterization. Note 3: Compliant jitter tolerance pattern in hex (CJTPAT): Pattern Sequence: 3E AA 2A AA AA 3E AA A6 A5 A9 87 1E 38 71 E3 87 1E 38 70 BC 78 F4 AA AA AA AA AA AA AA AA AA A1 55 55 E3 87 1E 38 71 E1 AB 9C 96 86 E6 C1 6A AA 9A A6 Note 4: Meets jitter output specifications with noise applied. Note 5: K28.7 Pattern: 00 1111 1000. Note 6: Compliant random pattern in hex (CRPAT): Pattern Sequence:
Repetitions: 6 1 41 1 12 1 1 1
Repetitions:
3E AA 2A AA AA 6 3E AA A6 A5 A9 1 86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 65 16 72 31 9A 95 AB 1 C1 6A AA 9A A6 1 Note 7: Parameter measured with 0.40UI deterministic jitter (patterns other than K28.7), and 0.20UI random jitter (BER = 10 -12) applied to the input. Jitter is in compliance with the inter-enclosure, fibre channel jitter tolerance (at compliance point R) and jitter output (at compliance point T) specifications (FC-PI rev 10.0). Output jitter is specified as an output total given a non-zero jitter input. Note 8: K28.5 Pattern: 00 1111 1010 11 0000 0101 Note 9: Random Pattern in hex (RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65 Note 10: Using differential drive over the entire input amplitude range. The input signal bandwidth is limited to 0.75 x (bit-rate) by a 4thorder Bessel Thompson filter or equivalent. Total jitter (TJ) is the range of the eye pattern where the BER exceeds 10-12. TJ can be estimated as TJ = DJ + 14 x RJ. DJ is deterministic jitter. RJ is a one sigma distribution (RMS) of random jitter. Note 11: Simulation shows peaking of 0.01dB max. Characterization results limited by test equipment.
4
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Dual-Rate Fibre Channel Repeaters
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
MAX3772-MAX3775
2.125Gbps JITTER TRANSFER vs. FREQUENCY
MAX3772-75 toc01
1.0625Gbps JITTER TRANSFER vs. FREQUENCY
MAX3772-75 toc02
2.125Gbps JITTER TOLERANCE
TOLERANCE EXCEEDS THE TEST EQUIPMENT'S GENERATION LIMIT
0 -1 JITTER ATTENUATION (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 10k 100k 1M 200mVp-p INPUT SIGNAL, PATTERN = CRPAT
0 -1 JITTER ATTENUATION (dB) -2 -3 -4 -5 -6 -7 -8 -9 200mVp-p INPUT SIGNAL, PATTERN = CRPAT
SINUSOIDAL JITTER (UIp-p)
CJTPAT PATTERN, DJ = 0.4UI RJ = 0.2UI
10
1 FIBRE CHANNEL MASK 0.1
10M
-10 10k 100k 1M 10M FREQUENCY (Hz)
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
1.0625Gbps JITTER TOLERANCE
MAX3772 toc04
OUTPUT EYE DIAGRAM AT OUT (2.125Gbps CRPAT)
MAX3772-75 toc05
OUTPUT EYE DIAGRAM AT OUT (1.0625Gbps CRPAT)
MAX3772-75 toc06
100
TOLERANCE EXCEEDS THE TEST EQUIPMENT'S GENERATION LIMIT
SINUSOIDAL JITTER (UIp-p)
CJTPAT PATTERN, DJ = 0.4UI RJ = 0.2UI
10 INPUT = 600mV DJ = 0.4UI RJ = 0.2UI 1 FIBRE CHANNEL MASK 0.1 10k 100k 1M 10M FREQUENCY (Hz) INPUT = 600mV DJ = 0.4UI RJ = 0.2UI
2.125Gbps OUTPUT JITTER BATHTUB PLOT
1E+00 1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 0 0.2 2.125Gbps CRPAT AT INPUT (DJ = 0.4UI, RJ = 0.2UI) 1E+00 1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 0
MAX3772-75 toc07
1.0625Gbps OUTPUT JITTER BATHTUB PLOT
1.0625Gbps CRPAT AT INPUT (DJ = 0.4UI, RJ = 0.2UI)
MAX3772-75 toc08
BIT ERROR RATE
BIT ERROR RATE
0.4
0.6
0.8
1.0
0.2
0.4
0.6
0.8
1.0
DATA-CROSSING TIME RELATIVE TO FIRST ZERO CROSSING (UI)
DATA-CROSSING TIME RELATIVE TO FIRST ZERO CROSSING (UI)
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MAX3772 toc03
1
1
100
5
Dual-Rate Fibre Channel Repeaters MAX3772-MAX3775
Pin Description
PIN 1 2 3, 6, 12 4 5 7, 8 9 10 11 13 14 15 16 EP NAME CF+ CFGND IN+ INVCC RATESEL OUTOUT+ CLKEN CLKCLK+ LOCK Exposed Paddle FUNCTION CDR Filter Capacitor Positive Connection. CF = 0.047F. CDR Filter Capacitor Negative Connection. CF = 0.047F. Electrical Ground Noninverted Data Input Inverted Data Input Supply Voltage Rate Select Pin. TTL low selects 1.0625Gbps operation. TTL high selects 2.125Gbps operation. Inverted Data Output Noninverted Data Output Clock Output Enable. TTL high enables the clock output. TTL low disables the clock output. Inverted Clock Output. Enabled when CLKEN is forced high; disabled when CLKEN is forced low. Noninverted Clock Output. Enabled when CLKEN is forced high; disabled when CLKEN is forced low. Frequency Lock Indicator. When data is present, a high level indicates the PLL is frequency-locked. The output of the LOCK pin may chatter when large jitter is applied to the input. The exposed paddle must be soldered to the circuit board ground for proper thermal performance.
Detailed Description
Figure 2 shows the functional block diagram of the MAX3772-MAX3775 fibre channel repeaters. They consist of a fully integrated PLL, CML input and output buffers, and a data latch. The PLL consists of a combined phase detector (PD) and frequency detector (FD), a loop filter, and a voltage-controlled oscillator (VCO). The input and output signal buffers employ lownoise CML architecture and are terminated on-chip.
VOUT+ 500mVp-p MIN 900mVp-p MAX VOUT-
(VOUT+) - (VOUT-) 1000mVp-p MIN 1800mVp-p MAX
Phase and Frequency Detector
The frequency difference between the VCO clock and the received data is derived by sampling the in-phase and quadrature VCO outputs on the edges of the input data signal. The FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the PD produces a voltage proportional to the phase difference between the incoming data and the internal clock. The PLL drives this error voltage to zero, aligning the recovered clock to the center of the incoming eye.
Figure 1. Example of Output Signal with Matched Output Loads
6
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Dual-Rate Fibre Channel Repeaters MAX3772-MAX3775
0.047F CF+ CFVCC
D
Q OUT+
IN+ PHASE/FREQ DETECTOR INOPTIONAL 100 OR 150 TERMINATION RATESEL CLKEN /2 0 VCC LOOP FILTER VCO 1 OPTIONAL 50 OR 75
OUT-
CLK+ CLKLOCK
Figure 2. Block Diagram
Loop Filter, VCO, and Latch
The phase detector and frequency detector outputs are summed into a loop filter. An external capacitor (between CF+ and CF-) is required to set the PLL damping factor. The fully integrated VCO contains an internal current reference and filter circuitry to minimize the influence of VCC noise. The VCO creates a clock output with frequency proportional to the control voltage applied by the loop filter. Data recovery is accomplished by using the recovered clock signal to latch the incoming data to the CML output buffers, significantly reducing output jitter.
See the Applications Information section for the functionality of the RATESEL pin.
Applications Information
Input and Output Terminations
Figures 3 and 4 show models for the MAX3772- MAX3775 inputs and outputs, including packaging parasitics.
VCC ESD STRUCTURES 1k 1.5nH IN+ 0.2pF 0.4pF 1.5nH 0.2pF 0.4pF
LOCK Output
An active high LOCK output monitor derived from the frequency detector indicates that the PLL is frequencylocked onto the input data. Without input data, the LOCK signal may settle high or low. The use of a lowpass RC filter is recommended to reduce the effects of chatter that could be caused by high input-jitter content. For optimum jitter performance, keep the load 15k on the output of the LOCK pin.
PACKAGE
RATESEL Input
The RATESEL input is used to select between input data rates of 2.125Gbps and 1.0625Gbps. This function allows the repeater to sample data at the correct data rate by selecting a divide-by-2 network, giving maximum jitter tolerance at both data rates. The loop bandwidth of the repeater scales with the selected frequency; i.e., the loop-bandwidth at an input rate of 1.0625Gbps is half that at the input rate of 2.125Gbps.
OPTIONAL VCC - 0.450V 50 OR 75
Figure 3. Input Structure 7
_______________________________________________________________________________________
Dual-Rate Fibre Channel Repeaters MAX3772-MAX3775
Layout Procedure
VCC PACKAGE OPTIONAL 50 OR 75
1.5nH OUT+ 0.4pF 1.5nH OUT0.4pF ESD STRUCTURES 0.2pF 0.2pF
The MAX3772-MAX3775 performance can be greatly affected by circuit-board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. All IN, OUT, and CLK pins should be connected with 0.1F coupling capacitors equivalent or better than X5R. A 0.047F capacitor should be used for the loop filter. If DC coupling is desired pay particular attention to the DC voltage and current requirements at the pins of interest (see DC Electrical Characteristics). The MAX3750/MAX3754/MAX3755 port bypass circuits can be DC-coupled to the Maxim dual-rate repeaters. The exposed paddle of the repeater must be connected to ground and should be soldered onto the circuit board for optimal thermal and electrical operation.
Pin Configuration
TOP VIEW Figure 4. Output Structure
CF+ 1 16 LOCK 15 CLK+ 14 CLK-
Control Functions
The MAX3772-MAX3775 have two control inputs: RATESEL and CLKEN. RATESEL is an input that sets the operational data rate for the repeaters. Table 1 shows the selected input data rates when using the RATESEL function. CLKEN is an input that can be used to enable or disable the output clock, as shown in Table 2.
CF- 2 GND 3 IN+ 4 IN- 5 GND 6 VCC 7 VCC 8
MAX3772 MAX3773 MAX3774 MAX3775
13 CLKEN 12 GND 11 OUT+ 10 OUT9 RATESEL
QSOP-EP*
Table 1. Input Data Rate Using RATESEL Function
RATESEL LEVEL GND VCC DATA RATE SELECTED 1.0625Gbps 2.125Gbps
*EXPOSED PADDLE MUST BE SOLDERED TO GROUND.
Selector Guide
PART MAX3772CEE MAX3773CEE DIFFERENTIAL INPUT TERMINATION 100 150 100 150 DIFFERENTIAL OUTPUT TERMINATION 100 100 150 150
Table 2. CLKEN Function
CLKEN LEVEL GND VCC CLOCK OUTPUT Disabled Enabled
MAX3774CEE MAX3775CEE
Chip Information
TRANSISTOR COUNT: 1280 PROCESS: Si
8
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Dual-Rate Fibre Channel Repeaters MAX3772-MAX3775
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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